1. Field of the Invention
The present invention relates generally to sense amplifiers, and more particularly, to a sense amplifier capable of preforming predetermined operations under no influence of variation of a power supply voltage. The present invention has particular applicability to static random access memories.
2. Description of the Background Art
Generally, semiconductor memories are widely used in various apparatuses such as a computer system and the like. A semiconductor memory has a great number of memory cells to and from which data is written and read. Out of the semiconductor memories, especially often used are dynamic random access memories (DRAM) and static random access memories (referred to as "SRAM" hereinafter). In general, a great number of memory cells are connected to bit lines in DRAMs and SRAMs. In a reading operation, a data signal stored in a memory cell is applied to a bit line to generate a small potential difference between bit lines. A sense amplifier senses the generated small potential difference and amplifies the same, so that the stored data i read. While the present invention is generally applicable to a sense amplifier for amplifying a small potential difference appearing between two signal lines or bit lines, a description will be made on SRAM as an example in the following.
In recent years, the requirements on both the enhancement of speed and low power consumption become more demanding, for which improvements have been made. For example, SRAMs, especially emitter coupled logic (referred to as "ECL" hereinafter) SRAMs operable at a high speed are used in order to constitute a cache memory for use in a large-scaled general-purpose computer. The ECLSRAMs are known as SRAMs using logic signals of a ECL level. A "H" level (logical high) of an input signal and a "L" (logical low) level thereof are defined as -0.9 volt and -1.7 volts in the ECL level, respectively.
FIG. 9 shows a conventional SRAM. In the drawing, in order to simplify the description, shown is a memory cell array having memory cells in four rows by four columns. The SRAM shown in FIG. 9 is described in, for example, U.S. Pat. No. 4,433,393. Referring to FIG. 9, the SRAM comprises an X decoder 1 responsive to an X address signal for activating word line driving circuits 2a-2d, word lines 3a-3d connected to outputs of the word line driving circuits 2a-2d, a Y decoder 4 responsive to a Y address signal for activating bit line selecting circuits 5a-5d, bit line pairs of 6a and 6b through 9a and 9b, and memory cells MC00-MC33 respectively connected between each of the word lines 3a-3d and each of the bit line pairs of 6a and 6b through 9a and 9b.
FIGS. 10 and 11 show examples of memory cells applicable to the SRAM, wherein FIG. 10 shows a high resistance load type NMOS memory cell and FIG. 11 shows a CMOS type memory cell.
Referring to FIG. 9 again, each of bit line load resistances 10a-13b is connected to each one end of the bit lines. The respective resistances 10a-13b are connected to a first power supply line (Vcc) 15 through a level shifter 14. Each of transfer gate transistors 16a-19b is connected to each of the other ends of the respective bit lines 6a-9b. The respective transistors of each transistor pair of the transistor pairs of 16a and 16b through 19a and 19b have gates connected to each output of the bit line selecting circuits 5a-5d, respectively. The respective bit line pairs of 6a and 6b through 9a and 9b are connected to I/O line pairs of 20a and 20b.
The I/O line pair of 20a and 20b is connected to two inputs of a sense amplifier 21. The sense amplifier 21 is connected to receive an activation signal SE generated from a sense amplifier selecting circuit 22. Two outputs of the sense amplifier 21 are connected to an output buffer 24 through a common data line pair of 23a and 23b. The output buffer 24 receives a signal of a SCL level through the common data line pair of 23a and 23b.
The other ends of I/O line pair of 20a and 20b are connected to a driving circuit 29 for driving the same. The driving circuit 29 includes four NMOS transistors 25 through 28 connected between a first power supply line 15 (Vcc) and a second power supply line (V.sub.EE) 30. The driving circuit 29 is connected to receive an output signal from a writing amplifier 31.
FIG. 12 shows a circuit diagram of the sense amplifier 21. Referring to FIG. 12, the sense amplifier comprises two npn transistors 33 and 34 and a current source 35. The transistor 33 has a base connected to the I/O line 20a and a collector connected to the common data line 23a. Similarly, the transistor 34 has a base connected to the I/O line 20b and a collector connected to the common data line 23b. Emitters of the transistors 33 and 34 are connected with each other, which is further connected to the current source 35. The current source 35 includes an NMOS transistor 36 connected to the second power supply line 30. The transistor 36 has a gate connected to receive the sense amplifier activation signal SE. The activation signal SE has a potential of an MOS level. Namely, the "H" level of the signal SE has a first power supply potential and the "L" level thereof has a second power supply potential.
Now, operations of the SRAM shown in FIG. 9 will be described. First, in a writing operation, an input data signal Din is applied to the writing amplifier 31 through an input buffer 31'. The writing amplifier 31 amplifies the input signal Din and applies the amplified signal to the driving circuit 29 through two signal lines 32a and 32b. The driving circuit 29 drives the I/O lines 20a and 20b in response to the received signal. The Y decoder 4 and the bit line selecting circuits 5a and 5d selectively turn on the transfer gate transistors 16a through 19b, so that voltages on the I/O line pairs of 20a and 20b are selectively applied to one pair of the bit line pairs of 6a and 6b through 9a and 9b. The X decoder 1 and the word line selecting circuits 2a-2d select one word line, whereby a signal based on the input data signal Din is written in a designated memory cell.
Now, a reading operation will be described in more detail. In the following, a description will be made of a case where data stored in the memory cell MC00 is read. The X decoder 1 applies a low level signal to two inputs of the word line selecting circuit 2a. Accordingly, the word line 3a attains a high level. High level signals are inputted to at least one of two inputs of each of the other word line selecting circuits 2b-2d, so that the other word lines 3b-3d attain a low level. As a result, only the word line 3a is selected.
Similarly, the Y decoder 4 applies low level signals to two inputs of the bit line selecting circuit 5a. Accordingly, the bit line selecting circuit 5a outputs a high level signal, so that the transfer gate transistors 16a and 16b are rendered conductive, which therefore means that the memory cell MC00 is selected.
When the memory cell MC00 is selected, a potential difference is generated between the bit lines 6a and 6b in, response to the data signal stored in the memory cell MC00. In order to transmit the data to the output buffer 24, the sense amplifier activating signal SE attains the high level. Accordingly, the transistor 36 provided in the current source 35 is turned on, so that the sense amplifier 21 is activated. The potential difference between the bit lines generated in response to the data stored in the memory cell MC00 appears on the I/O line pair of 20a and 20b through the transfer gate transistors 16a and 16b. The potential difference is amplified by the sense amplifier 21 and thereafter is applied to the output buffer 24. While the above-described reading operation is carried out, both of the outputs 32a and 32b of the writing amplifier are fixed to a low level. On the other hand, in writing, a potential on one bit line to which a low level data signal is written is made to be of a low potential and a potential on the other bit line is made to be of a high potential.
In case none of the memory cells connected to one of the I/O line pairs of 20a and 20b is selected, all the word lines 3a-3d and all the outputs of the bit line selecting circuits 5a through 5d attain a low level, so that none of the data signals stored in the memory cells is applied to the I/O line pair of 20a and 20b. On this occasion, since the sense amplifier 21 does not need to be activated, a low level sense amplifier activating signal SE is applied in order to reduce power consumption. Accordingly, the current source 35 is turned off to render the sense amplifier 21 non-activated.
FIG. 13 shows a circuit diagram of the output buffer 24. Referring to FIG. 13, the common data lines 23a and 23b are connected to nodes Na and Nb, respectively. npn transistors 61 and 62 clamp potentials of the nodes Na and Nb. The clamped potentials are determined by a diode 63 and a constant current source 64. Accordingly, although signal currents flow in the common data lines 23a and 23b, potentials thereon do not fluctuate.
The signal currents from the sense amplifier flow to the common data line 23a through, for example, the transistor 62. Accordingly, a current signal is converted into a voltage signal by a resistance 66, and the converted voltage signal is applied to a base of the transistor 76. The signal currents flowing in the common data line 23b are also converted into voltage signals by a resistance 65 and the converted voltage signals are applied to a base of the transistor 67. An npn transistor 76, a diode 68, an npn transistor 69 and a resistance 70 constitute an emitter-follower circuit. Accordingly, a level of a voltage of a node N2 is shifted by a voltage V.sub.BE between a base and an emitter of the transistor 76. The level-shifted voltage is applied to an ECL circuit in the succeeding stage through a node N3.
The ECL circuit comprises npn transistors 71, 72, 73 and 75 and resistances 74 and 77. The transistor 75 has a current drivability large enough to drive other circuits connected to an output terminal Dout. Inputs of the ECL circuit, that is, bases of the transistors 71 and 72 are connected to the nodes N3 and N4, respectively. The transistor 73 and the resistance 74 constitute a constant current source. Accordingly, in response to potentials of the nodes N3 and N4, a voltage signal is applied to a base of the transistor 75 through a common connection node N5 between the resistance 77 and the transistor 72. As a result, an output data signal is outputted through the transistor 75 and the terminal Dout.
Conventionally, two voltage levels are used for a power source of the ECLSRAM. More specifically, -0.5 volt and -5.2 volts are used as a power source V.sub.EE (Vcc is set to 0 volt). Additionally, since such semiconductor memories as SRAMs are used in various apparatuses as described above, a power supply voltage level often fluctuates. If the power supply voltage level changes or fluctuates, problems arise.
Namely, in the sense amplifier shown in FIG. 12 voltage between a gate and a source of the transistor 36 in the current source 35 changes as a voltage on the power supply line 30 changes or fluctuates. This causes the currents to be changed which flow in the common data lines 23a and 23b through the transistors 33 and 34. The change of the signal currents flowing in the common data lines 23a and 23b cause erroneous reading of data in the output buffer shown in FIG. 13. Namely, the change of the signal currents flowing in the common data lines 23a and 23b signifies that the currents flowing in the transistors 61 and 62 change. As a result, potentials at the nodes N1 and N2 change by the effects of the resistances 65 and 66. Particularly, the potentials at the nodes N1 and N2 sometimes drop to be lower than the potential at the node N, Whereby the transistors 61 and 62 operate in a saturation region. Accordingly, a switching speed of the transistors 61 and 62 is reduced. In addition, it is pointed out that change or fluctuation of the potentials at the nodes N1 and N2 leads to erroneous reading of a data signal. This is possible because the transistors 67 and 76 operate in response to the potentials at the nodes N1 and N2, so that the ECL circuit in the succeeding stage might operate erroneously.